This invention relates generally to logic level translators and more particularly, it relates to a logic translator circuit for converting transistor-transistor-logic (TTL) level signals to current-mode-logic (CML) level signals which have a higher speed of operation, a reduction in power dissipation and immunity from ground bounce noise.
As is generally well known in the art, various types of digital logic circuitry are widely utilized in the area of computer data processing systems in different parts of the processing system. In order to transfer data from one part of the processing system having one logic type (i.e., TTL) of integrated circuit devices to another part having another logic type (i.e., CML/ECL) of integrated circuit devices, there is often required a translation from the one logic type to the other logic type. Since many of these processing systems are designed with both TTL and CML/ECL logic circuits, there has arisen a need in the industry for interface circuits such as TTL-to-CML/ECL translators so that these two different types of logic circuits will be compatible with each other.
TTL logic circuits typically operate on logic signal levels below +0.8 volts and above +2.0 volts while CML logic circuits typically operate on different logic levels between -1.0 to -1.6 volts. While the precise levels utilized in the CML/ECL logic circuits differ among manufacturers, the voltage swing between the two CML logic levels is commonly less than the voltage swing between the two TTL logic levels. Further, the TTL circuit makes use of a positive power source voltage VCC (i.e., +5.0 volts) and a ground potential TGND). On the other hand, the CML circuit makes use of a negative power supply voltage VEE (i.e., -5.2 volts) and a ground potential CGND). Both ground potentials TGND and CGND are typically at zero volts.
Prior art translators use diodes and other semiconductor devices to obtain a fixed voltage drop to translate from one type of binary signal level to another type of binary signal level. However, these prior art translators suffer from the disadvantage in that they used a common ground which is shared by both the TTL input and CML output signals. For example, the TTL input signals and the CML output signals would share the same bus line as a common ground. Such a logic level translator 10 of the prior art is shown in FIG. 1 and has been labeled "Prior Art." This prior art translator can be found in "Analysis and Design of Digital Integrated Circuits" written by David A. Hodges and Horace G. Jackson, p. 296, published in 1983 by McGraw-Hill, Inc.
This prior art translator 10 includes a TTL input stage 12 and a CML output stage 14. The TTL input stage 12 is coupled between a positive power supply voltage VCC (i.e., +5.0 volts) and a ground potential GND. The TTL input stage 12 receives TTL logic levels at input nodes A and B. The CML output stage 14 is coupled between a negative power supply potential VEE (i.e., -5.2 volts) and the same ground potential (GND). The CML output stage 14 can deliver both an OR output at the collector of the transistor Q5 and a NOR output at the collector of the transistor Q4. As a result, any TTL currents flowing in the commonly shared ground bus (GND) will produce noise signals (referred to as ground bounce noise) in the CML output stage 14 of the translator. Also, any variations in the positive power supply potential VCC used in the TTL input stage 12 would be coupled to the CML output stage 14 of the translator. Further, the input threshold of the TTL input stage depends directly on the value of the voltage V.sub.r at the base of the transistor Q5 and the value of the voltage V.sub.BB at the base of the transistor Q2. Moreover, the use of a resistor R3 to perform a level shifting limits the transient current, thereby causing propagation delays which reduces the speed of operation of the translator.
Accordingly, it would be desirable to provide an improved TTL-to-CML translator circuit which is immune to ground bounce noise but yet has a higher switching speed with reduced power dissipation. The logic level translator circuit of the present invention represents an improvement over the translator circuit 10 of FIG. 1 which isolates the TTL and CML ground bus lines so as to reduce the noise that may be transferred between the TTL ground bus and the CML ground bus.